STARC Integrates Cadence Encounter Solution for Complex, Large-Scale Designs

Industry Consortium Certifies Cadence Encounter Solution for Complex Designs over 20 Million Gates

SAN JOSE, Calif., Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, announced that the Japanese electronic design consortium STARC is implementing a Cadence® flow for semiconductor designs larger than 20 million gates. The new STARCAD-CEL V3.0 methodology for large-scale design was defined by the consortium to describe a comprehensive, RTL-to-GDSII design methodology for quickly designing semiconductor systems of this size. After extensive evaluation, the Cadence Encounter® platform and methodology met all necessary STARC requirements.

“The intent of the STARCAD-CEL V3.0 design flow is to qualify for STARC member companies the most comprehensive and efficient flow for large scale designs,” said Nobuyuki Nishiguchi, vice president and general manager, Development Department 1 at STARC. “Cadence was able to complete the entire end-to-end solution with the turnaround time and memory footprint results that met and exceeded our criteria.”

Included in the STARCAD-CEL V3.0 flow are technologies for RTL-to-GDSII digital implementation, low power design, and design for manufacturing supported by Cadence solutions.

Key Cadence technologies within the flow are the Cadence Encounter Digital Implementation System, which provides a scalable multiprocessing backplane necessary to enable a faster turnaround time as well as a full suite of capabilities for low power and advanced node; Cadence Encounter Conformal® ECO Designer, which enables significantly faster design changes without manual effort and reduces the risk of missing critical bugs; and, Cadence Encounter RTL Compiler, which enables large-scale top-down synthesis with superior quality of results and run-time acceleration for designs of up to 40 million gates. Cadence Encounter Timing System and QRC Extraction are also evaluated and integrated in the STARCAD-CEL V3.0 flow.

“Over the course of this year, Cadence engineers have consistently delivered highly integrated design flows and methodologies that are now the backbone of IC design projects the world over,” said Dr. Chi-Ping Hsu, senior vice president of digital implementation research and development at Cadence. “This declaration by STARC is clear evidence that in a sea of competing offerings, Cadence is able to deliver a complete end-to-end solution and methodology with the turnaround time and memory integration necessary for large scale, complex designs.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.