Architect Labs Unveils Redwood: The World’s First Fully AI-Designed AI Chip That Runs AI Models

Architect Labs announced today that its AI system generated and fully verified, end-to-end from a human-written specification, a production-worthy AI accelerator called Redwood. With only two human architects writing the architectural specification, the AI system designed and fully verified the chip in under two weeks, while also co-designing the firmware, custom kernels, and mapping modern AI models to the chip. The AI accelerator is currently deployed on an FPGA platform, running inference on multi-billion parameter models like Llama and Qwen.

This marks the first time in the semiconductor industry’s 80 year history that an AI system has autonomously designed a production-worthy AI chip capable of running AI models itself. This achievement creates a direct feedback loop between AI workloads and the silicon optimized to run them: better AI models can now design better hardware, and better hardware can run better models, at a pace no traditional chip design cycle can match. The performance results suggest Redwood is more than just a proof of concept. Projected onto Samsung 8 nm, the same process class as NVIDIA’s Jetson Orin Nano, Redwood delivers 1.75x the throughput at 1.9x lower power, a 3.4x improvement in performance per watt against a measured Jetson baseline running the same AI models.

Closing the loop between AI and silicon

Designing a chip is historically one of the most gated efforts in modern technology. Designing even a single chip can take years of development, cost hundreds of millions in investment, and with a shrinking pool of experts across architecture, design, and verification, new silicon designs are becoming concentrated inside a handful of giant companies. At that pace, the loop between a workload and the hardware built for it barely turns at all. Traditionally, teams adopt general purpose hardware and spend their effort reshaping the workload to fit, quantizing and restructuring AI workloads to suit silicon that was specified years before the workload matured.

Redwood presents a paradigm shift for the industry. The hardware was designed for the software rather than the software fitted to the hardware, with kernels, firmware, and Register-Transfer Level (RTL) design co-developed and optimized together instead of handed down from software to hardware in sequence. And the loop now closes on itself: Architect Labs’ AI system generated and fully verified an AI accelerator running AI models more efficiently with better performance and power. With Architect Labs’ autonomous full-stack optimization approach, better AI models can be co-designed with the underlying hardware, and better hardware can be derived to run AI models more efficiently, building a recursive self-improvement loop towards the industry’s path to abundant intelligence.

“Chips were designed by one or two engineers when I started in this business four decades ago. Since then, design complexity, time, and risk have grown exponentially. Even with every advance in EDA tools and technologies, a single chip program consumed multiple years and enormous engineering teams,” said Sunil Shenoy, former Senior Vice President of Engineering at Intel. “Redwood is a genuine paradigm shift, and a concrete benchmark of the frontier of what is possible. Architect Labs is democratizing capabilities that were the exclusive domain of a few giants, at a speed I would not have believed possible. Their approach promises to take hardware back to the future.”

Inside Redwood: A Frontier AI Accelerator

Redwood is an end-to-end AI inference platform built for physical AI: robots, drones, and edge devices that must run modern AI models in real time on a strict power budget. At its heart is a scalable mesh of matrix and vector compute engines, connected by a purpose-built on-chip network and coordinated on hardware to keep every engine fed. The full pipeline of modern AI inference, including attention with KV caching and on-the-fly quantization, runs natively on the chip with no round trips to a host processor. Redwood was built entirely from scratch including the compute engines, on-chip network, firmware, and custom kernels were all designed together and optimized against each other, so the silicon matches the way the models actually run. Redwood can also be scaled into or integrated in a larger datacenter SoC or deployed in production as a standalone chiplet.

Key statistics on autonomous Redwood design:

• Autonomous design and verification: 100% of the RTL, UVM verification environments, formal verification, firmware, drivers, and custom compute kernels were generated end-to-end by Architect Labs’ AI system from a human-written specification in under two weeks with two human architects working on the project.
• Signoff-grade verification, zero hardware bugs: Every block, from individual IP to the full SoC, closed at over 95% code and functional coverage using commercial EDA tools, Architect Labs’ proprietary formal engine, and hardware-in-the-loop validation. The first RTL drop from simulation to FPGA platform contained zero bugs.
• Running real AI models on real hardware: Redwood Nano is deployed on an AMD Versal FPGA at 250 MHz, executing real-time, single-batch inference on open-weight models including Qwen. Architect Labs ran live hardware demos at this year’s Design Automation Conference (DAC), one of the only companies at the show demonstrating AI designed accelerator running inference on models live…
• Outperforming today’s leading edge AI silicon: Projected onto Samsung 8 nm, the same process class as NVIDIA’s Jetson Orin Nano, Redwood delivers 1.75x the throughput at 1.9x lower power, a 3.4x improvement in performance per watt, against a measured Jetson baseline running the same model. These projections are calibrated from direct FPGA measurements, not simulation alone.
• Architectural iteration in days, not quarters: Any change to the high-level specification results in fully regenerated, reverified, and redeployed hardware in under 48 hours, with the exception of SoC-level runs bounded by EDA tool runtimes.
• Recursive self-improvement: An AI model deployed on Redwood exposed as an API endpoint discovered timing and kernel optimizations for the accelerator itself, at near-zero inference cost, closing the loop of AI and the silicon that fuels it.

Full details on the chip and some insights into how it was built here: architectlabs.com/redwood-paper

“Every era of computing has been enabled by the underlying hardware, but also gated by who could afford to build the silicon for it, and ,” said Steve Jang, Founder and Managing Partner at Kindred Ventures. “The Redwood chip is early proof that the gate can come down: two people - starting with a written specification and target AI model - used Architect Labs’ system to fully design, verify and deploy a competitive AI accelerator in weeks. Whether you are a frontier research lab, robot maker, or a cloud operator, the concept of making your own custom silicon purpose-built for your product or platform is now becoming a reality.”

A fundamentally new way of designing software to silicon

Architect Labs’ end-to-end AI system reasons across the entire stack at once, from model to kernels to firmware to RTL, rather than siloed, sequential optimizations in traditional chip design flows. This fundamentally new approach of designing computing systems allows software to be co-optimized with the underlying silicon, all the way to tape-out with iterations in weeks, rather than months. With this transformative approach, an operation that would have cost thousands of software cycles gets built directly into a datapath. A scheduling problem the hardware would otherwise have carried in silicon gets handed to the compiler instead. Tradeoffs like these have always been the right ones to make. What has never existed is the ability to make them, verify them, and see the result running in hardware in days. Redwood is a validation of Architect Labs’ approach that can now be scaled to more complex hardware.

“Three decades ago, foundries like TSMC made world-class manufacturing available to anyone with a design, and the fabless industry with companies like NVIDIA, Broadcom, and Apple was born,” said Ebrahim Hussain, co-founder and CEO of Architect Labs. “In a similar fashion, we are pioneering the designless semiconductor industry, where chips like Redwood are co-designed and co-evolved with the workloads they run. We envision that software companies with intensive workloads or specialized AI models can get co-designed custom silicon, without having to build a large design team, stake a decade on an architectural bet, or fall back to off the shelf general purpose solutions, leaving performance, power and cost savings on the table. Every workload that matters deserves its own custom chip. We are building towards a future where they can have one.”

Architect Labs is already applying the same approach with Fortune 500 partners, co-designing custom chip designs at the speed of software and compressing programs that would traditionally run for months into ones measured in weeks. Redwood is the first public demonstration of what that makes possible.

About Architect Labs

Architect Labs co-designs, verifies, and tapeout custom chips end-to-end using AI, enabling companies to transform demanding workloads into production-ready silicon while dramatically accelerating chip development timelines. By making custom silicon more accessible, Architect Labs aims to enable a future where every important workload can run and co-evolve alongside the hardware purpose-built for it. Beginning with chip design and expanding across the broader compute stack, the company is reimagining how computing systems are built for the age of superintelligence. Architect Labs was founded by Ebrahim Hussain and Aaditya Subedi and is based in Palo Alto, California. Learn more at architectlabs.com.

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