DAPDNA-IMS, a new Dynamically Reconfigurable Processor

DAPDNA-IMS, a Dynamically Reconfigurable Processor for
Image Processing Applications, Sample Shipped

Improved Processing Element Architecture from its Successful
Predecessor, DAPDNA-2
Fast Design Iteration Using Data Flow C Language

September 5-Tokyo, Japan. IPFlex Inc. today announced it has started shipping DAPDNA*-IMS, a dynamically reconfigurable processor** (DRP) for image processing in office automation applications such as Multi Function Printers. DAPDNA-IMS includes hardware accelerators for image processing such as JPEG. An integrated development environment for DAPDNA-IMS, “DAPDNA-FW II v3.0,” is also released. The software toolset includes Data Flow C*** compiler enabling users program hardware at a C-level abstraction, greatly reducing the design time.

The second off-the-shelf DRP chip from IPFlex Inc. is a DAPDNA-IMS targeted for image processing in office automation applications. Office automation market, which includes products such as multi function printers, faces shorter lifecycles for the products, and at the same time, needs to satisfy customers who require customized products, leading to small lot productions. DAPDNA-IMS targets this difficult market with a highly flexible programmable logic chip based on the DAPDNA architecture. The DAPDNA architecture has been proven to be highly effective in image processing applications with its predecessor, DAPDNA-2, which has become the de facto processor in image processing for industrial inspection systems.

[Features of DAPDNA-IMS] DAPDNA-IMS is a DRP that can change its hardware functionality in one clock (5 nano-seconds) thereby performing multiple functions that traditionally required multiple chips. The chip includes a 32-bit RISC core as a controller and a heterogeneous matrix of 955 16bit processing elements (PEs). The matrix can change its functionality even when the system is in operation, adapting to changes in the environment as necessary.

With DAPDNA-IMS, the mix of PEs is highly tuned for various kinds of image processing, especially office automation applications. The chip includes useful functional components such as line buffers and Huffman decoding hardware accelerators. Targeting large volume markets, DAPDNA-IMS is priced competitively.

[DAPDNA-IMS Specifications]

DAP: 32 bit RISC processor, 8KB Instruction cache, 8KB Data cache
DNA: 955 dynamically reconfigurable 16 bit PEs in a 2-D matrix, 3 DNA Configuration memory banks:
- 1 foreground bank and 2 background banks
- Can load additional DNA Configurations from main memory
Ext. Interface:
- Direct I/O: 200MHz (Max, sync to ext. clock), 16 bit, 4 ch I/O total 1.6GByte/s. Can be used to connect multiple DAPDNA-IMS chips
- DDR2 SDRAM: 266MHz, 64 bit DDR2 SDRAM I/F total 4.25GByte/s., 1GB max
- PCI Express: PCI Express rev1.0a compliant (x4)
- ROM: Boot and Program Serial ROM (SPI)
- Ext. Interrupt: 8
- Other: UART, GPIO
Clock: 266MHz
Power: 3.3V(I/O) 1.8V(I/O) 1.2V（core）
Package: TE-BGA, 1156 pin


[Integrated Development Environment for DAPNDA-IMS Released]
An integrated development environment for DAPDNA-IMS is also released. DAPDNA-FW II v3.0 is a high-performance software toolset which covers all application development processes from algorithm design to actual hardware implementation. The main feature is the Data Flow C language, which lets its users write algorithms in an extended C language. The algorithm is compiled automatically by the DFC Compiler onto the chip. Useful features such as wave viewer, memory viewer, resource manager and power manager are also included to aid in debugging process.
A new feature on the toolset is called “pre-fit whole chip simulation.” With this feature, a user can simulate the entire chip’s functionality before mapping the algorithm onto hardware thereby allowing complete validation of functionalities among the DAP RISC processor, the reconfigurable DNA Matrix, and external interfaces. The toolset also works with the DAPDNA-2 processor.

[Ordering DAPDNA-IMS】
IPFlex accepts orders and starts shipping sample chips and DAPDNA-FW II v3.0 today.
IPFlex accepts orders for DAPDNA-EB6 evaluation board. For details, please contact IPFlex Global Sales Department.

[Terminology]
* DAPDNA: Digital Application Processor / Distributed Network Architecture.
** Dynamically Reconfigurable Processor (DRP): A processor capable of changing chip circuitry dynamically.
*** DFC: Co-developed with Celoxica Ltd.

[About IPFlex]
IPFlex develops high performance, multifunctional dynamically reconfigurable processors (DRP) based on its internationally patented DAPDNA technology. IPFlex also provides design tools, evaluation boards, and peripheral interface products for the processors. The DAPDNA series of DRPs combined with the design tools based on the Software-To-Silicon ® concept aim to greatly reduce the design iteration while providing flexibility in hardware that lets systems adapt to the changes in the operating environment.

IPFlex and its partners in the DAPDNA Partner Program together provide optimal solutions for customers in inspection systems, image processing, network security, and high performance computing.

IPFlex, DAPDNA, and Software-to-Silicon are registered trademarks of IPFlex in Japan. Other corporate and product names are the trademarks or registered trademarks of their respective owners.


Information on this release is accurate as of the date of the release and may be changed or updated without notice.

Contact Information

Keis Ide

Global Sales Div.

IPFlex, inc.

Contact via E-mail