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Agilent Technologies Adds Industry-First Exerciser x16, Interposer Probing to E2960B Series for PCI Express 1.0, 2.0


Complete, Scalable Test Portfolio for All Speed Classes and Link Widths Enables Engineers to Master Transition to Next-Generation PCI Express

Agilent Technologies Inc. (NYSE: A) today introduced the industry’s first exerciser x16 and slot interposer probing solution for its E2960B Series for PCI Express(r) (PCIe) 2.0. The Agilent E2960B Series now addresses the industry’s need for a scalable and integrated analyzer and exerciser solution that provides non-intrusive measurement of PCIe signals, generic stimulus and cross-system analysis across all link widths and speed classes of PCI Express 1.0 and 2.0.

The trend to high-speed serial technology continues with the introduction of the next-generation PCIe protocol. PCIe 2.0 doubles the speed from 2.5 Gb/s to 5 Gb/s. This satisfies the increased need for bandwidth of high-performance applications such as graphics, and also allows existing applications to keep the bandwidth while moving to a reduced pin count. Agilent’s E2960B Series for PCI Express is the leading tool for engineers to master the transition to the next generation, as it provides both an analysis solution and a stimulus solution, which is a must for efficient bring-up of any PCI Express device or system.

For engineers analyzing PCI Express systems, the right choice of reliable probing solutions is vitally important. In addition to its proven Midbus Probe 2.0 with Soft Touch technology, Agilent offers the Agilent N5315A solid slot interposer for PCI Express 2.0, available in all link widths up to x16.

Furthermore, the enhanced E2960B Series software suite covers transaction viewing, which provides a more condense view on traffic, summarizing all packets that belong to a transaction in a single yet expandable line. Based on Agilent’s sophisticated search engine, it enables ad-hoc debugging with almost immediate feedback, avoiding long waiting cycles during debug sessions.

The Agilent PCIe exerciser is the only tool for testing both PCI Express devices or systems when engineers require 1) a stimulus solution that enables fast, efficient feedback on the link training behavior of a PCIe device, and 2) a powerful solution that drives the device to its edge.

Transaction layer testing and data link layer testing enables simultaneous use of the LTSSM (Link Training and Status State Machine) tester and the exerciser. The LTSSM tester x1 to x16 generates training sequences at speed on all lanes, which allows effective link-negotiation testing using predefined tests, now extended to cover a larger part of the LTSSM.

The exerciser x1 to x16 is a fully featured and freely programmable stimulus solution that enables root-complex emulation, end-point emulation and add-in card testing at all link widths. The exerciser also offers data memory compare, power management support and DLLP transmission with errors functionality, enabling additional classes of validation test for PCI Express 2.0.

The Agilent E2960B Series for PCI Express 2.0 can scale to meet current needs with PCI Express 1.0 and extend the functionality as needed to suit PCI Express 2.0. The modular nature of the E2960B Series protects the customer’s investment as its supports a variety of building blocks such as analyzer, exerciser, two speed classes (Gen2 ready at 2.5 Gb/s and full at 5 Gb/s), all link widths (x1, x4, x8, x16), the extended Protocol to Logic (P2L) for cross-triggering, marker correlation, and flags between protocol and logic analyzer.

“We are excited to expand our offering for the industry-leading E2960B Series for PCI Express,” said Siegfried Gross, vice president and general manager of Agilent’s Digital Verification Solutions Division. “With outstanding probing solutions combined with the advanced exerciser capabilities and expanded software features, we are putting our customers in the driver’s seat for PCI Express design and development up to 5 Gb/s speed.”

The solutions will be demonstrated at the PCI-SIG Developer Conference in San Jose, Calif., on May 21, Booth 2.


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