Deliver Your News to the World

Texas Instruments Qualifies 65 Nanometer Chip Process And Is Moving To Volume Manufacturing


Rapid Ramp to Production Expected in Early 2006

DALLAS (December 6, 2005) - Texas Instruments Incorporated (NYSE: TXN) (TI) announced it has qualified its advanced 65-nm process technology only eight months after delivering first samples of a wireless device and is moving to volume manufacturing. The TI 65-nm process delivers more processing performance for advanced applications in a smaller space without increasing power consumption. TI is leading the volume ramp to production for 65nm process technology with volume product delivery across its targeted markets, including wireless communications.

“TI’s model of driving our own in-house process technology development and initial production ramp in one TI fab and then fanning out to multiple fabs and foundries allows us to quickly achieve very high volumes for our customers,” said Dr. Hans Stork, chief technology officer, Texas Instruments. “In this business, building some sample parts is good, but the competitive advantage goes to the supplier who can first deliver millions of high quality products.”

TI first disclosed details around its advanced 65-nm CMOS process in early 2004, and announced sampling of the wireless digital baseband processor in March 2005. The process technology doubles transistor density over the company’s 90nm process, shrinking equivalent designs by half and boosting transistor performance by up to 40 percent. In addition, TI’s technology significantly reduces leakage power from idle transistors while simultaneously integrating hundreds of millions of transistors that support both analog and digital functions in System on Chip (SoC) configurations.

“Our relationship with Texas Instruments is based on close technology collaboration”, said Tommi Uhari, VP, Wireless Platforms, Nokia. “Early access to such solutions as TI’s 65-nm process helps Nokia get to market faster with the most advanced products and capabilities that our customers require.”

Managing Power Through SmartReflexTM Technologies

Today’s advanced multimedia and high-end digital consumer electronics have increased processing demands and the focus on low power semiconductor technology development. To address the challenge, TI has implemented its SmartReflexTM power and performance management technologies in its 65-nm platform in order to offer a combination of intelligent and adaptive silicon, circuit design and software designed to solve power and performance management challenges at smaller process nodes.

By closely monitoring circuit speed, SmartReflex technologies can dynamically adjust voltages to meet exact performance requirements without sacrificing overall system performance. As a result, minimum power is used for each operating frequency, extending battery life and reducing the amount of heat produced by the device.

Other techniques at 65-nm reduce power consumed by transistors when they are idle, including times when mobile phones are in standby mode waiting to receive calls. These innovations include back-biasing of SRAM memory blocks and retention flip-flop circuitry that allows voltages to drop extremely low without requiring a rewrite of logic or memory content. Together, these SmartReflex advancements can deliver up to a 1000 times reduction in power leakage.

Delivering Design Flexibility and System Optimization

TI continues to offer several process technology recipes, optimized to balance the unique needs of end products or applications. This includes the very low power offering that extends battery life in a range of portable products such as 3G mobile devices, digital cameras and audio players with increasingly sophisticated multimedia features. A mid-range offering supports DSP-based products and TI’s high performance ASIC library geared toward communications infrastructure products. The highest performance version of TI’s 65-nm process supports server-class microprocessors.

The 65-nm process includes up to 11 layers of copper interconnect integrated with a low k dielectric, OSG, with a k of 2.8 - 2.9. Other improvements include an induced strain on the transistor channel during chip processing to increase electron and hole mobility; nickel silicide to lower both gate and source / drain resistance, and ultra-shallow source / drain junctions.


This news content was configured by WebWire editorial staff. Linking is permitted.

News Release Distribution and Press Release Distribution Services Provided by WebWire.