Cadence Kick-Starts UVM Adoption with Open-Source Reference Flow Contribution to UVM World
UVM Reference Flow Enables Users to Rapidly Learn and Apply the Universal Verification Methodology
SAN JOSE, Calif., Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced the industry’s most comprehensive open-source reference flow for system-on-chip (SoC) verification using the Universal Verification Methodology (UVM) standard. The unique flow enables engineers to adopt advanced verification techniques with reduced risk and deployment effort while meeting critical time-to-market requirements.
In support of the Cadence EDA360 strategy for delivering SoC Realization capabilities, UVM Reference Flow 1.0 provides a proven SoC design and UVM-compliant testbench components as open source for users to learn and apply advanced verification techniques. Users will be able to download the environment and instrument the UVM verification components to the design. This provides practical hands-on experience for applying the technology in an executable form when run on a UVM-compliant simulator. All code is provided in clear-text form so users can make modifications, apply different verification scenarios and precisely see the results of those changes.
The UVM, adopted recently by the Accellera standards organization, is built largely on the framework of the Open Verification Methodology (OVM) that Cadence® co-developed.
“Cadence has a rich history of improving functional verification productivity,” said Olivier Haller, verification manager at STMicroelectronics. “The reference flow will make it easier and faster to adopt UVM for verifying our chips. ST plans to use this UVM reference flow to demonstrate our own advanced methodologies as well as for internal training purposes. There is now a very complete reference available for both IP- and SoC- level verification challenges.”
SoC Realization is one of the key capabilities outlined in the EDA360 vision, with IP and SoC verification as critical steps. UVM Reference Flow 1.0 provides a real-world example that addresses key challenges engineers face. It provides the ability to exercise verification techniques, validate verification re-use, manage low-power modes typical in today’s SoCs, ensure verification scalability from block to system and improve verification productivity. Based on the proven Incisive® Verification Kit, the reference flow includes both design and verification IP from Cadence that was converted to open source and contributed to www.UVMworld.org, a Web site supporting the new UVM standard.
“With today’s wireless and consumer chip designs becoming increasingly complex, development teams are under growing pressure to apply more effective verification methods and technology,” said Thomas L. Anderson, verification product management director at Cadence. “The UVM Reference Flow enables the SoC Realization capabilities of EDA360 by creating a comprehensive environment to ease adoption of advanced techniques.”
The new UVM Reference Flow 1.0 will be featured at the Design Automation Conference (DAC), scheduled for June 13 to 18 in Anaheim, Calif. More information on the conference can be found at www.dac.com.
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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