NEC Electronics Announces Development of a New Low-Resistance Cu Interconnects Technology for High-Frequency Operations in Low-Power 40nm CMOS Devices
New Partially-Thickened Local Structure Halves the Interconnect Resistance
KAWASAKI, Japan, NEC Electronics Corporation (TSE:6723) today announced that it has developed an extremely low-resistance copper (Cu)-interconnect with partially-thickened local (PTL) structure. The new PTL interconnect technology has been developed to address the resistivity increase of Cu-interconnects, which degrades the radio frequency (RF) performance of analog transistors. By implementing the newly developed PTL interconnect technology into the latest 40-nanometer (nm) node low-power CMOS LSIs, NEC Electronics achieved excellent RF performance suitable for next-generation wireless communication technologies, including long-term evolution (LTE) and WiMAX specifications.
Features of the newly developed technology are as follows:
* (1) Without any change in the in-plain scaling, an extremely low-resistance Cu interconnect is formed by selectively thickening specific parts of a Cu interconnect where low-resistance is strongly required. By applying full low-k (FLK) dielectric materials in addition to the new PTL technology, a Cu interconnect can reduce parasitic capacitance and yet still achieve low resistance.
* (2) By implementing the PLT-interconnect structure to connect the gate-electrode as an input ports of analog transistors for RF signals, NEC Electronics succeeded in reducing input resistance of the Cu interconnect by 50 percent. The RF performance thereby enhanced by 30 percent to achieve maximum oscillation frequency (fMAX, Note 1) of over 200 gigahertz (GHz) in the low-power 40nm-node CMOS LSIs, making them applicable for the next-generation low-power broadband wireless communication systems, while preserving the low-power operation in logic functions.
* (3) The new low-cost fabrication process suppressing micro-loading (Note 2) effect has been also developed by NEC Electronics adopting both the new slit-shaped PTL-interconnect as well as the columnar-shaped Cu contact-plugs, required to connect the CMOS transistors and the Cu interconnects.
As miniaturization of CMOS devices progresses, it is necessary to reduce the cross-section area and the space of the Cu interconnects. However, smaller area simultaneously results in increased parasitic resistance as well as parasitic capacitance, degrading the RF performance required for next-generation broadband wireless communications. To resolve these issues, it is crucial to lower the gate-electrode interconnect as an input signal port in analog transistor. NEC Electronics has developed a “low-k Cu dual-damascene (DD) contact (CT) interconnect” technology, in which the insulating dielectrics is changed from silicon-oxide (SiO2) to low-k dielectrics (SiOCH) and the contact metal is alternated from high-resistive tungsten (W) to Cu. Eventually a Cu interconnect with Cu CT plugs was buried in FLK dielectrics over the CMOS transistor. However, the RF performance improved by only 10 percent due to the low-k Cu DD-CT interconnect with the conventional tiny Cu-CT plugs that could not reduce the resistance of the gate-electrode interconnect sufficiently.
NEC Electronics therefore developed the PTL technology that selectively thickens specific parts of the “Low-k Cu DD CT” structure three-dimensionally, while the other area remained connected only with the Cu CT plugs with low parasitic capacitance. By the mixed-configuration of the Cu PTL interconnect structure and the Cu CT plugs on a SoC chip: (1) the Cu CT plugs are applied to the logic device areas where capacitance reduction is strongly required, and (2) the PTL interconnect is implemented to analog areas, such as gate-electrodes, where resistance reduction is essential for flexible design layout The newly developed PTL interconnect is ideal for low-power mixed-signal CMOS LSIs with digital/analog functions.
NEC Electronics’ flexible-layout PTL interconnect technology reduces contact resistance and local-interconnect resistance and provides analog interface performance suitable for ultra high-frequency and broadband CMOS wireless terminals, embedded DRAMs and multi-core SoCs, while preserving low power consumption. NEC Electronics aims to advance its research and development activities in this area.
NEC Electronics presented the results of this research at the International Electron Devices Meeting 2009 (IEDM 2009) held from December 7 through December 9, in Baltimore, U.S.
About NEC Electronics
NEC Electronics Corporation (TSE: 6723) specializes in semiconductor products encompassing advanced technology solutions for the high-end computing and broadband networking markets; system solutions for the mobile handset, PC peripheral, automotive and digital consumer markets; and multi-market solutions for a wide range of customer applications. NEC Electronics Corporation has subsidiaries worldwide including NEC Electronics America, Inc. and NEC Electronics (Europe) GmbH. More information about NEC Electronics worldwide can be found at www.necel.com.
Maximum Oscillation Frequency (fMAX): The number of maximum frequency MOS transistor can oscillate. The figure is used to evaluate the high frequency analog performance of the transistors.
Micro-loading: An undesirable phenomena in reactive-ion-etching (RIE) process, where etching time, or essentially etching rate, for opening patters into dielectrics is fluctuated as a function of the relative area and its density. This is caused by dependence of flux-density of etchant ions on the opening-area and its density of opening patters such as tiny columnar-shaped and large slit-shaped contacts.
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