Synopsys IC Compiler Enables Fully Automated 65-Nanometer Implementation Flow For ARM Cortex-A8 Processor
Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, and ARM [(LSE: ARM; (Nasdaq: ARMHY)], today announced the immediate availability of a fully automated implementation flow enabled by Synopsys IC Compiler for high-performance and low-power applications. The Galaxy™ Design Platform RTL-to-GDSII flow for the synthesizable ARM® Cortex™-A8 processor includes DC Topographical technology, the DFT MAX solution and the latest physical design technology available in IC Compiler. This portable Synopsys flow, along with the ARM processor and physical IP, delivers a 5-10x improvement in designer productivity compared to the original optimized, semi-custom approach. The flow has also delivered more than 1000 DMIPS at 500MHz performance in a 65-nanometer (nm) low-power process technology and is capable of achieving over 1700 DMIPS at 850MHz for advanced consumer applications when targeted at high-performance 65-nm process technologies.
“The ARM and Synopsys technical collaboration has resulted in a widely deployable implementation flow for the Cortex-A8 processor with clear time-to-market savings,” said John Cornish, vice president of marketing, Processor Division, ARM. “With many customers focused on increased productivity and meeting tight schedules, the Synopsys Galaxy implementation flow for the Cortex-A8 processor will enable customers to achieve a high-performance and low-power design point with a small team and limited resource investment.”
The Cortex-A8 processor, ARM’s first high-end application processor based on the ARMv7 architecture, features support for TrustZone® technology, Thumb®-2 instructions, Jazelle®-RCT technology and the powerful ARM NEON™ signal processing extensions that are targeted at the next-generation enriched multimedia and gaming platforms.
Building on experience from the optimized semi-custom implementation design flow for the Cortex-A8 processor, ARM and Synopsys have created a fully automated synthesizable Galaxy implementation flow. The new approach enables a small team of engineers with a standard ASIC design background to achieve the required performance for next-generation high-performance, low-power applications within three months. The easy-to-use implementation flow leverages ARM physical IP optimized for the Cortex-A8 processor while enabling broader design portability across both libraries and process technologies (90-nm, 65-nm and 45-nm).
“The key to addressing high-performance and low-power needs of the wireless and consumer markets is the concurrent optimization capability in design tools,” said Bijan Kiani, vice president of marketing, Synopsys Implementation Group. “Delivering a 500 MHz low-power Cortex-A8 processor and an 850 MHz high-performance version is a strong testimonial to the strength of our technology and close collaboration with ARM.”
The automated implementation flow for the synthesizable Cortex-A8 processor was validated using the ARM Advantage™-HS standard cells and optimized Advantage Random Access Memory (RAM) instances for 65-nm LP technology to achieve both high performance and low power. The combination of an easy-to-use implementation flow, a high-quality processor and physical IP enables customers to deliver proven results with best-in-class productivity. Designers can combine the flow with the ARM physical IP, optimized for the Cortex-A8 processor, or use the flow with their own physical IP libraries.
ARM and Synopsys, a member of the ARM Connected Community, will present a technical paper on this flow at the San Jose Synopsys Users Group (SNUG) on Monday, April 2nd 2007 and at the Design, Automation and Test (DATE) conference on Wednesday, April 18th 2007.
The automated implementation flow for the Cortex-A8 processor (scripts and documentation) is available immediately from Synopsys. In addition, Synopsys offers consulting services to help accelerate the adoption and implementation of advanced methodologies, including high-performance and low-power design techniques for ARM processor-based designs, including those based on the Cortex-A8 processor. The synthesizable Cortex-A8 processor, Advantage-HS standard cells and optimized Advantage RAM instances for target 65LP processes are immediately available from ARM.
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