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Agilent Technologies Offers Only Complete Jitter Tolerance Test for Next Generation of Forwarded-, Embedded-Clock Designs


J-BERT Provides Complete Jitter Tolerance Characterization, Compliance Testing for PCI Express(r) 2.0, USB 3.0, QuickPath Interconnect, Hypertransport 3 and FB-DIMM 2 Devices.

SANTA CLARA, Calif., DesignCon 2009, Booth 305.- Agilent Technologies Inc. (NYSE: A) today announced that its new J-BERT N4903B high-performance serial BERT offers the only complete jitter tolerance testing for high-speed digital interfaces operating up to 12.5 Gb/s. Design and test engineers can now accurately characterize and test compliance of next generation multi-gigabit serial bus devices, such as PCI Express (PCIe) 2.0, USB 3, QuickPath Interconnect (QPI), Hypertransport 3 and fully-buffered DIMM 2 (FB-DIMM 2), receiving the most integrated and accurate characterization to enable more robust designs.

Forward clocking architectures, such as QPI, Hypertransport, and FB-DIMM 2, operate with forwarded clocks running at half the data rate. This causes additional test challenges to the design teams when characterizing these receivers under real-world stress conditions. Agilent’s J-BERT N4903B characterizes the jitter tolerance and margins of such receivers by providing half-rate clocks with variable duty-cycle distortion to emulate effects of non-ideal clocking. It allows users to inject jitter on the forwarded half-rate clock and on data signals with adjustable phase relations. This allows the most accurate characterization enabling more robust designs.

Higher data rates of next-generation high-speed embedded clocked computer and video buses, such as PCI Express 2.0, USB 3, DisplayPort and SATA 6G, require sophisticated jitter injection and signaling during the test-and-validation phase. The new Agilent N4903B addresses these needs by offering even more calibrated and built-in jitter injection and signaling capabilities.

“We are very proud to offer the industries’ leading jitter tolerance test solution,” said Jorgen Beck, general manager of Agilent’s Digital Photonic Test product line. “By addressing the latest test requirements from embedded and forward clock architectures to our J-BERT platform, we continuously demonstrate our commitment to enable R&D and validation teams to release the next generation of robust high-speed digital interfaces for the computer, video and communication industries.”

Benefits of the Agilent J-BERT N4903B High-Performance Serial BERT include:

* ability to emulate worst-case conditions by generating half-rate clocks with variable duty cycle and jitter for forward-clocked devices;
* most integrated and calibrated jitter sources, with selectable random jitter with PCIe 2.0-compliant spectral distribution, single- and two-tone periodic jitter, spread spectrum clock (SSC) and residual SSC, BUJ, built-in ISI, and sinusoidal interference;
* compliant jitter injection for testing the latest serial bus receivers , such as PCIe 2.0, USB 3.0, SATA and DisplayPort;
* accurate TJ measurements with built-in CDR with tunable loop bandwidth;
* easier adoption to device under test by emulating electrical idle conditions and offering variable output voltage levels on supplementary outputs (trigger output and aux data output);
* faster execution of long test sequences with 60 block pattern sequencer; and
* upgrade path from Agilent’s N4903A to N4903B, protecting investments.

Additional information about Agilent’s J-BERT N4903B is available at images are available at

A video about the J-BERT N4903B is available at

U.S. Pricing and Availability

The Agilent J-BERT N4903B will be available for ordering March 2009. Pricing for the Agilent J-BERT N4903B high-performance serial BERT with built-in tunable CDR starts at $139,000 for the 7 Gb/s version, and $179,000 for the 12.5Gb/s version. Agilent’s J-BERT N4903B is the replacement product for the N4903A.


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