Kaben Wireless Silicon Achieves up to 7X Performance Boost with Cadence Virtuoso Accelerated Parallel Simulator
Leading RFIC IP Provider Cites Success While Catching Flaws Early in the Design Process Enabling First-Pass Silicon Tapeout
SAN JOSE, Calif., Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that Kaben Wireless Silicon has achieved dramatic performance boosts while running top-level simulations using the Cadence® Virtuoso® Accelerated Parallel Simulator (APS). Kaben, a leading provider of RFIC semiconductor IP for next-generation wireless communication, also credits the Virtuoso Accelerated Parallel Simulator with enabling engineers to find and resolve design issues that they believe they would have missed without the performance and capacity delivered by APS.
The simulator was introduced in December, and to date Kaben has achieved impressive results, including one case where Kaben achieved a 7.6 times performance boost with four threads over the baseline SPICE simulator on a pre-layout PLL design with fewer than 5,000 devices. In the case of a post-layout PLL design with 328,000 devices dominated by parasitics, the Virtuoso Accelerated Parallel Simulator ran the complete simulation without reducing the design net list in four days with full SPICE accuracy compared to a previous solution where they were not even able to run the simulation.
“Because of its quick run time and high-capacity, the Virtuoso Accelerated Parallel Simulator helped our team find design issues early on in the verification phase, then quickly fix them and run another iteration of verification,” said Tom Riley, chief technology officer of Kaben Wireless Silicon. “The ability to perform high-capacity post-layout simulations quickly, for fully functional and integrated transceiver IP, with full SPICE accuracy and scalable performance across a multi-compute platform is a real enabler for our efforts to deliver turnkey wireless applications to our customers.”
The Virtuoso Accelerated Parallel Simulator also enables Kaben to run simulations at new levels of abstraction. Kaben engineers can get more coverage across various corners and conditions in less time than required by previous solutions. The simulator can be accessed through a flexible token-based licensing model.
The Virtuoso Accelerated Parallel Simulator delivers the full accuracy of the industry reference Cadence Virtuoso Spectre® Circuit Simulator. Developed to solve the largest and most complex analog and mixed-signal designs across all process nodes, it consists of a combination of proven Cadence simulation technologies and a breakthrough parallel circuit solver, along with a newly architected engine that efficiently harnesses the power of multiprocessing computing platforms. The result is a circuit simulator with an accuracy and use model identical to the Virtuoso Spectre Circuit Simulator, delivering significantly improved single-thread performance and scalable multi-thread performance.
“Kaben Wireless Silicon’s designs are, by necessity, very complex components, and therefore comprehensive simulations are a necessity to help ensure they meet customer specifications,” said Zhihong Liu, corporate vice president of Cadence. “Kaben is seeing firsthand how the Virtuoso Accelerated Parallel Simulator delivers comprehensive simulation, and helps ensure market opportunities are realized.”
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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