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Toshiba achieves higher hole mobility for future generation CMOS technology by twisted Direct Silicon Bonding technology


TOKYO--Toshiba Corporation today announced that, together with IBM Corporation, it has developed a higher performance CMOS FET, a high priority for advanced system LSI. The new technology matches the highest possible performance, and opens the way for further advances in process technology. Toshiba and IBM announced the achievement on June 19, at the VLSI Symposia 2008, in Honolulu, Hawaii, U.S.A.

High performance, low power and scalability have won CMOS technology a central place in semiconductor technology, a position now under threat as CMOS scaling edges towards fundamental physical limits that inhibit further advances in transistor performance and migration to finer process technology. As a consequence, the industry is seeking new ways to overcome these challenges. These approaches include adoption of new materials such as High-K and metal gates and new structures. Another way to improve performance is to increase the mobility of electron , or holes, through device channels; direct silicon bonding (DSB) wafers, a bulk CMOS hybrid type wafer that bonds (100) and (110) substrates, is a recognized candidate for advancing this approach.

In developing the new methodology, obtaining standard (100) silicon wafers by rotating the plane of the (100) layer by 45 degrees and thinning the DSB layer of the (110) substrate, Toshiba and IBM have successfully integrated technology with improving 10% delay of the ring oscillator than achievement compared to conventional DSB substrate 0 degree (100) wafers, which bonds to a wafer two silicon substrates, a (100) and a (110) substrate. The development improved the ring oscillator delay to a point of 30% than the standard (100) wafers. The achievement can be integrated with technologies that can reach even higher advances.

CMOS makes use of two types of transistors: positively-charged field effect transistors (PFETs), and negatively charged FETs (NFETs). For PFETs, hole mobility is known to achieve a higher performance on a substrate with (110) surface-orientation than on a substrate with (100) surface-orientation. However, for NFETs, electric charge mobility deteriorates on a substrate with (110) surface-orientation, compared to mobility on a substrate (100) surface-orientation. Toshiba and IBM achieved the newly announced performance using new hybrid-orientation technology fabricated on a hybrid substrate with different crystal orientations to achieve significant PFET performance improvement without any deterioration in NFET performance.

Toshiba is studying various technologies for future advanced devices, and believes that the new technology is a step forward to more powerful practical devices.


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