PULLNANO Consortium Reports Breakthrough Results for 32/22nm CMOS Technology Generations

PULLNANO, a project sponsored by the European Commission within the 6th Framework Program (FP6), has reported several important results related to the future-generation 32nm and 22nm CMOS technology platforms, including the realization of a functional CMOS SRAM (Static Random Access Memory) demonstrator built using 32nm design rules. PULLNANO is a collective effort of 38 European partner organizations, including leading chip manufacturers, industry-orientated research institutions, universities and SMEs (Small and Medium Enterprises). The aim of PULLNANO is to develop advanced knowledge that will enable European chip manufacturers to maintain their strong presence in the worldwide microelectronics industry from 2010, when the 32nm generation of CMOS technology is expected to be commercially available.


SRAM is required in most of the complex System-on-Chip (SoC) devices that are built with leading-edge CMOS technologies and the demonstration of a functional SRAM is therefore an important milestone. The PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of the transistors used in the 45nm technology node. The transistors are built using a low power consumption approach based on Fully Depleted Silicon On Insulator (FDSOI) coupled with a gate stack composed of a high-K gate dielectric and a single metal electrode stack. This is believed to be the first time that such a compact SRAM cell has been fabricated using FDSOI, high-k dielectric and metal gate together. PULLNANO is ahead of schedule in reaching this first milestone and also expects to demonstrate an even smaller cell before the end of the year.

At the IEEE International Interconnect Technology Conference, held in June 2007 in San Francisco, PULLNANO partners also reported results relating to the Back-End Of the Line (BEOL) part of the PULLNANO project. BEOL is the stage in the chip fabrication process when the active components, such as the transistors, are interconnected with metal wiring. PULLNANO has demonstrated that the material and integration schemes used in the 45nm generation can be modified to provide a robust solution at 32nm and has also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called “air gap” technique.

In the field of Modeling and Simulation, PULLNANO academic partners have developed innovative approaches to predicting the device performance for the 32nm and 22nm CMOS generations. These include new simulators that allow the evaluation, ahead of actual fabrication, of the impact of the new technology options such as the channel material and the choice of high-k dielectric. The selection of the best compromise between physical accuracy and computational effort has led to very efficient and effective ways to account for the quantum mechanical effects which govern the operation of these advanced devices. This work contributes to enriching the standard ITRS (International Technology Roadmap for Semiconductors) device performance evaluation tool

“The 32nm generation will be a pivotal node for semiconductor manufacturers because we are dealing with layers only a few atoms thick, where quantum mechanical effects become more and more important,” said Gilles Thomas, STMicroelectronics R&D Cooperative Programs Manager and coordinator of the PULLNANO project. “The successful industrialization of the 32nm and 22nm generations will require a deep understanding of the physical issues as well as the most advanced modelling and simulation tools and the PULLNANO consortium is well advanced in developing these.”