Cadence to Showcase Comprehensive PCI Express IP and Verification Solutions at PCI-SIG 2015
Cadence Design Systems, Inc. (NASDAQ: CDNS) announced its participation at PCI-SIG Developers Conference 2015, to be held from June 23-24, 2015 in Santa Clara, California. Cadence plans to showcase its PCI Express® 2.0 multi-protocol PHY, PCI Express 4.0 SerDes, PCI Express 4.0 controller solution, as well as the Indago™ Protocol Debug App.
Visitors to the Cadence® booth (#8) can see the following demonstrations:
- PCIe® 2.0 Multi-Protocol PHY for Mobile Applications
- PCIe 4.0 SerDes for Server Applications
- High-Performance PCIe 4.0 Controller Solution
- Indago Protocol Debug App
Cadence is scheduled to deliver two papers at the conference sessions:
- Emulating a PCIe 4.0 Controller on a Real System by Gopi Krishnamurthy, Digital IP Group Architect (Wednesday, June 24, 2015, 10:30-11:30 a.m., track 4, session 2)
- Bridging the Simulation and Measurement Gap by Ken Willis, Product Engineering Director at Cadence and Sarah Boen, Product Marketing Manager at Tektronix (Wednesday, June 24, 2015, 2:30-3:30 p.m., track 3, session 5)
June 23-24, 2015
Santa Clara Convention Center, Booth 8
5001 Great America Parkway
Santa Clara, CA 95054
Cadence (NASDAQ: CDNS) enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
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