Hitachi Raises System-Level Simulation Performance 100x with Cadence Palladium Transaction-Based Acceleration
Cadence Verification Acceleration Technology Compresses Network System Verification Schedules and Boosts Quality and Reliability
SAN JOSE, Calif., Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that engineers at Hitachi, Ltd. successfully implemented a new system-level verification environment for Ethernet routing/switching products using the Cadence® Incisive® Palladium® transaction-based acceleration technology. The new environment, based on the Palladium emulation system and the Incisive Enterprise Simulator, increases performance by potentially 100 times over previous HDL simulation. The environment supports constrained-random test generation and offers greater control and visibility over the simulation, debugging and verification process.
Hitachi and Cadence engineers collaborated on the integration of Palladium transaction-based acceleration (TBA) technology into Hitachi’s future LSI development flow. Hitachi’s original environment was classic HDL simulation based, with signal-based communication among the testbench components, coverage-driven Hitachi-proprietary verification IP (VIP), and the design under test (DUT). To create the new environment, Hitachi engineers used a two-step process. First, they modified their VIP to add transaction-level interfaces. Then they adapted the bus-functional models in their VIP, and together with the DUT synthesized/mapped those into their Palladium emulation system. This resulted in a total performance increase of over 100 times. This new environment including TBA will allow the Hitachi engineers to run variable network traffic and validate their complex network components on the Palladium system. Besides Palladium TBA, Hitachi engineers also leveraged other Palladium features for in-circuit emulation, such as Cadence SpeedBridge® Adapters for Ethernet and ARM Logic Tiles, to facilitate emulation of verification interfaces and accelerate performance.
“Hitachi has been using Cadence Palladium technology successfully for both in-circuit emulation and simulation acceleration for many years, and we are very pleased with the recent improvements in Palladium TBA related to setup/compile time, debugging support, performance and ease of use,” said Toru Hiyama, General Manager, MONOZUKURI Innovation Operation, Hardware MONOZUKURI Division at Hitachi, Ltd. “Our engineers were able to implement and run the new TBA environment with very impressive results in terms of performance, flexibility and scalability. We expect this new flow will compress our overall verification and validation schedules significantly.”
“Our Palladium transaction-based acceleration delivers the time-to-market and debugging benefits that enable leading companies like Hitachi to validate their complex designs thoroughly and with confidence,” said Ran Avinun, product management group director for System Design and Verification at Cadence. “Palladium TBA is our latest example of capabilities to help customers accelerate full-system verification for critical projects.”
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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