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Energy-Efficient, High Performing and Stylish Intel–Based Computers to Come with Intel® Core™ Microarchitecture


INTEL DEVELOPER FORUM, San Francisco, Calif., March 7, 2006 – Intel Corporation today disclosed details of its forthcoming Intel® Core™ microarchitecture, a new industry–leading foundation for Intel”s multi–core server, desktop and mobile processors for computers later this year. The first Intel Core microarchitecture products built on Intel”s advanced 65nm process technology will deliver higher–performing, yet more energy–efficient processors that spur more stylish, quieter and smaller mobile and desktop computers and servers that can reduce electricity and real–estate associated costs, and provides critical capabilities such as enhanced security, virtualization and manageability for consumers and businesses.

Justin Rattner, Intel Senior Fellow and chief technology officer, explained that the Intel Core microarchitecture is the foundation for delivering greater energy–efficient performance first seen in the Intel® Core™ Duo processor. It builds on the power–saving philosophy begun with the Mobile Intel® Pentium®–M processor microarchitecture and greatly expands it, incorporating many new and leading–edge innovations as well as existing Intel® Pentium® 4 processor technologies such as wide data pathways and streaming instructions. Intel expects processors based on the Intel Core microarchitecture, using Intel”s industry–leading 65nm manufacturing technology, to start shipping in the third quarter of 2006.

“The Intel Core microarchitecture is a milestone in enabling scalable performance and energy efficiency,” said Rattner. “Later this year it will fuel new dual–core processors and quad–core processors in 2007 that we expect to deliver industry leading performance and capabilities per watt. People will see systems that can be faster, smaller and quieter with longer battery life and lower electric bills.”

In his keynote, Rattner showed how the Conroe desktop processor could provide roughly a 40 percent boost in performance and a 40 percent decrease in power as compared to Intel”s current high–performing Intel® Pentium® D 950 processor.** He also discussed significant gains in the Enterprise and Mobile areas as well.

Enhancing Users” Experiences
By providing higher performance, greater energy efficiency and more responsive multitasking, the Intel Core microarchitecture will enhance users” experiences in all environments – in homes, businesses, and on the go. “ In the home, these include higher performing, ultra–quiet, sleek and low–power computer designs, and new advances in more sophisticated, user–friendly entertainment systems.

For businesses, it will reduce space, cooling requirements and electrical demand in server data centers, as well as increase responsiveness, productivity and energy efficiency across client and server platforms.
For mobile users, the Intel Core microarchitecture means responsive computing performance combined with leading battery life in a variety of small form factors that enable world–class computing “on the go.”

Other Keynote Speakers at IDF
Rattner also outlined the other Intel executive keynotes that followed his opening presentation: Pat Gelsinger, senior vice president, general manager, Digital Enterprise Group on how Intel will build on the Intel Core microarchitecture to deliver superior computing performance and power efficiency for PCs, servers and the core of the network infrastructure while reducing the total cost of IT ownership; Sean Maloney, executive vice president, general manager, Mobility Group on Intel”s mobile future, highlighting new innovations in mobile devices and broadband wireless technology; and Don MacDonald, vice president, general manager, Digital Home Group on how Intel® Viiv™ technology is emerging as the foundation for a digital home where consumers can access their entert! ainment anytime, anywhere, on their choice of devices.

New Intel® Core™ Microarchitecture Features
Several advances mark the new microarchitecture:

Intel® Wide Dynamic Execution –– Delivers more instructions per clock cycle, improving execution and energy efficiency. Every execution core is wider, allowing each core to complete up to four full instructions simultaneously using an efficient 14–stage pipeline.
Intel® Intelligent Power Capability –– Includes features that further reduce power consumption by intelligently powering on individual logic subsystems only when required.
Intel® Advanced Smart Cache –– This includes a shared L2 cache to reduce power by minimizing memory traffic and increase performance by allowing one core to utilize the entire cache when the other core is idle.
Intel® Smart Memory Access –– Yet another feature that improves system performance by hiding memory latency and thus optimizing the use of data bandwidth out to the memory subsystem.
Intel® Advanced Digital Media Boost –– Now all 128–bit SSE, SSE2 and SSE3 instructions execute within only one cycle. This effectively doubles the execution speed for these instructions which are used widely in multimedia and graphics applications.

About the Intel Developer Forum
IDF is the direction–setting communications and computing industry program for Intel architecture–based design, development and solutions. Launched in 1997 as a gathering of 200 developers in San Francisco, IDF is a growing, worldwide program attended by more than 25,000 technology experts annually. IDF helps key players expand their knowledge of cutting–edge technologies, gain tools for building enterprise–level solutions and make powerful connections. Visit for more information.

Intel, the world’s largest chip maker, is also a leading manufacturer of computer, networking and communications products. Additional information about Intel is available at

Intel, the Intel logo, Centrino, “Intel. Leap ahead.,”, “Intel. Leap ahead.” logo, Intel Viiv and Intel Inside are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

* Other names and brands may be claimed as the property of others.

**performance based on estimated SPECint*_rate_base2000. Actual performance may vary. Power reduction based on TDP.


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